Senior ASIC Verification Engineer
NVIDIA is actively searching for talented Senior Verification Engineers to ensure the integrity and excellence of our industry-leading SoCs and GPUs. Joining this team means stepping into a dynamic, innovation-driven environment where your contributions will shape products spanning consumer graphics, autonomous vehicles, and the rapidly evolving realm of artificial intelligence. Our global team is dedicated to redefining the boundaries of technology, working collaboratively to advance what's possible today and set the foundation for tomorrow's computing platforms. We are a team of hardworking engineers working across the micro-architecture, design, verification, implementation, and post silicon validation of groundbreaking NVIDIA automotive and gaming console chips. We specifically focus on the backbone IPs for an ARM based System on-chip.
What You’ll Be Doing:
- As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading SoCs, ensuring first-pass silicon success.
- Lead the verification of the ASIC design, architecture, golden models, and micro-architecture using sophisticated methodologies such as UVM.
- Deeply understand the design, define the verification scope, and develop robust verification infrastructure to verify the correctness of complex logic.
- Collaborate with architects, designers, and both pre- and post-silicon verification teams to drive comprehensive coverage.
- Innovate by bringing AI and LLM-driven workflows into the verification cycle to optimize testbench generation, debug productivity, and coverage closure.
What We Need to See:
- BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science; advanced degrees (MS, PhD) are a plus.
- 5+ years of experience in ASIC verification-related fields at both the IP and SoC level.
- Proven experience in building UVM testbenches from scratch and applying constrained random methodology in a production environment.
- High proficiency in C/C++ with the ability to develop architectural golden models and hardware-software co-verification tests.
- Deep domain knowledge in Low-Speed IOs (QSPI, UART, I2C), High-Speed IOs (Ethernet), AXI/APB interconnects, DMA controllers, and Memory Controllers.
- Expert skills in assertion-based design checks (SVA), code coverage, functional coverage, and formal test plan documentation.
- Strong debugging and analytical skills with a methodical approach to resolving complex SoC-level corner cases.
- Professional-grade scripting abilities in Python, Perl, or TCL to automate build flows and regressions.
Ways to Stand Out from the Crowd:
- Advanced UVM architecture knowledge and large-scale SoC verification experience is a plus!
- A forward-thinking mindset with a demonstrated ability to use AI tools to accelerate engineering tasks.
- Experience with Testbench Build flows, Makefiles, and version control (Perforce).
- Ambitious, highly motivated, and a strong desire to work as a collaborative teammate in a fast-paced environment.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until August 24, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About NVIDIA
NVIDIA is a computing platform company operating at the intersection of graphics, HPC, and AI.
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