Staff Analog Design Engineer, SerDes Clocking

d-Matrix · Santa Clara, California · Posted 2026-08-19

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Role Overview

This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro.

What You Will Do

Own transistor-level design of low-jitter frequency synthesis — LC and/or ring PLL, including loop filter, charge pump or digital loop, VCO, and divider chain.

Own the phase interpolator and phase rotation scheme, including INL/DNL, glitch behavior, and interpolation resolution against the CDR's needs.

Design high-frequency clock distribution across the SerDes macro: buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation.

Define and verify CDR architecture and loop dynamics — bandwidth, jitter tolerance, jitter transfer, lock acquisition, and frequency offset tracking — modeling loop behavior in MATLAB, Python, or equivalent, and correlating against transistor-level and silicon results, in coordination with datapath and DSP owners.

Build phase-noise and jitter budgets for the link and own the analysis showing where jitter originates.

Build the verification environment for your blocks — PSS/HB and transient noise analysis, PVT corner coverage, Monte Carlo, and post-layout back-annotated simulation — and provide behavioral and Verilog-A models for full-chip verification.

Drive layout of your blocks in deep sub-micron nodes, with particular attention to inductor and VCO layout, shielding, symmetry, and supply/substrate isolation.

Take your blocks through silicon bring-up and bench characterization — phase noise, jitter tolerance, lock range — and correlate measured results against simulation.

What You Will Bring

BS/MS/PhD in Electrical Engineering, with 5+ years of hands-on analog and mixed-signal circuit design experience.

Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link.

Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory, along with working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer.

Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation.

Circuit design experience in advanced FinFET or GAA process nodes, using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation).

Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs.

Preferred

Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including clocking architecture choices specific to short-reach, low-energy-per-bit links.

Forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR.

Digital and hybrid PLL/CDR implementations, including the digital calibration around them.

Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7.

Experience porting a clocking block across process nodes, with a realistic sense of what that effort costs.

Participation in or contribution to standards bodies.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

About d-Matrix

D-Matrix is a computing platform that targets artificial intelligence inferencing workloads in the datacenter.