Tech Lead Engineer, Design Verification
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments.
Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver highly reliable PCIe and UALink connectivity products that keep AI accelerators, memory, and compute resources operating at scale.
Key Responsibilities
- Verification Strategy and Planning
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.
- Review designs and verification plans with architecture and RTL teams to identify corner cases early.
- Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics.
- Environment Development and Execution
- Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
- Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCIe behavior.
- Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.
- Partner with RTL and firmware teams to refine interfaces, improve observability, and resolve functional issues.
- Coverage, Quality, and Silicon Readiness
- Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones.
- Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.
- Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness.
- Communicate verification status, risks, and recommendations to technical stakeholders and project leadership.
Basic Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 5–8 years of experience in design verification for complex ASICs or SoCs.
- Hands-on experience with SystemVerilog and UVM-based verification environments.
- Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
- Familiarity with simulation, waveform-debug, regression, and coverage tools.
- Strong technical leadership, debugging, communication, and collaboration skills in a fast-paced product development environment.
Preferred Qualifications
- Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience verifying PCIe, UALink, UCIe, or other high-speed connectivity and switching protocols.
- Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
- Experience with Python, PowerShell, or Tcl for verification automation and regression infrastructure.
- Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.
Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
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